1. Field of the Invention
The present invention relates to the field of semiconductor manufacturing techniques and, more particularly, to a technique for fabricating copper interconnects by electroless metallization.
2. Prior Art
In the manufacture of devices on a semiconductor wafer, it is now the practice to fabricate multiple levels of conductive (typically metal) layers above a substrate. The multiple metallization layers are employed in order to accommodate higher densities as device dimensions shrink well below one micron design rules. Thus, semiconductor "chips" having three and four levels of metallization are becoming more prevalent as device geometries shrink to sub-micron levels.
One common metal used for forming metal lines (also referred to as wiring) on a wafer is aluminum. Aluminum is used because it is relatively inexpensive compared to other conductive materials, it has low resistivity and is also relatively easy to etch. Aluminum is also used as a material for forming interconnections in vias to connect the different metal layers. However, as the size of via/contact holes is scaled down to a sub-micron region, the step coverage problem appears, which has led to reliability problems when using aluminum to form the interconnection between different wiring layers. The poor step coverage in the sub-micron via/contact holes result in high current density and enhance the electromigration.
One approach to providing improved interconnection paths in the vias is to form completely filled plugs by utilizing metals, such as tungsten. Thus, many semiconductor devices fabricated utilizing the current state of VLSI (Very Large Scale Integration) technology employ the use of aluminum for the wiring and tungsten plugs for providing the interconnection between the different levels of wiring. However, there are disadvantages of using tungsten as well. Mostly, tungsten processes are complicated and appreciably expensive. Tungsten also has high resistivity. The Joule heating may enhance the electromigration of adjacent aluminum wiring. Furthermore, tungsten plugs are susceptible to the presence of voids and form poor interface with the wiring layers which usually result in high contact resistance. Another solution for the plug interconnects is the use of aluminum plugs, which can be fabricated by chemical vapor deposition (CVD) or physical vapor deposition (PVD) at elevated temperatures. The CVD aluminum is proven to be expensive and the hot PVD aluminum usually requires very high process temperatures that sometimes is not compatible with the manufacturing of integrated circuits.
One material which has received considerable attention as a replacement material for VLSI interconnect metallizations is copper. Since copper has better electromigration property and lower resistivity than aluminum, it is a more preferred material for interconnect (plugs and wiring) formation than aluminum. In addition, copper has improved electrical properties than tungsten, making copper a desirable metal for use as plugs. However, one serious disadvantage of using copper metallization is that it is difficult to etch. Thus, where it was relatively easier to etch aluminum or tungsten after depositing them to form wiring lines or plugs (both wiring and plugs are referred to as interconnects), substantial additional cost and time are now required to etch copper.
One typical practice in the art is to fabricate copper plugs and wiring by inlaid (Damascene) structures by employing CMP (see for example, U.S. Pat. No. 4,789,648). However, since copper diffuse/drift easily in inter-level-dielectric (ILD) materials, such as SiO.sub.2 based ILD materials, copper interconnect structures must be encapsulated by diffusion barrier layers. (See for example, "Barriers Against Copper Diffusion into Silicon and Drift Through Silicon Dioxide;" Shi-Qing Wang; MRS Bulletin; August 1994; pp. 30-40; "Encapsulated Copper Interconnection Devices Using Sidewall Barriers;" Donald S. Gardner et al.;1991 VMIC Conference; Jun. 11-12, 1991; pp. 99-108; and "Copper Interconnection with Tungsten Cladding for ULSI;" J. S. H. Cho et al.; VLSI Symposium; 1991; pp. 39-40). Accordingly, it is a common practice to use diffusion barrier metals, such as titanium nitride (TiN) or titanium tungsten (TiW), as well as dielectric barrier materials, such as silicon nitride (SiN), to encapsulate copper. Typically, the use of diffusion barrier material to encapsulate copper is not limited to the copper-ILD interface, but also to interfaces with other metals as well, if there are other such metals.
To replace the tungsten and/or aluminum interconnect structures with copper interconnects in VLSI (or ULSI) manufacturing, another important factor to consider is the process cost. One technique of depositing copper, as well as other metals, is the use of electroless deposition (See for example, "Electroless Cu for VLSI;" James S. H. Cho et al.; MRS Bulletin; June 1993; pp. 31-38; "Selective Electroless Metal Deposition For Integrated Circuit Fabrication;" Chiu H. Ting et al.; J. Electrochem. Soc., 136; 1989; p. 456 et seq.; "Selective Electroless Metal Deposition For Via Hole Filling In VLSI Multilevel Interconnection Structures;" Chiu H. Ting et al.; J. Electrochem. Soc., 136; 1989; p.462 et seq.; and U.S. Pat. No. 5,240,497).
In comparison to other copper deposition techniques, electroless copper deposition is attractive due to the low processing cost and high quality of copper deposited. The equipment for performing electroless metal deposition are relatively less expensive, as compared to other semiconductor equipment for depositing metals, and the technique allows for batch processing of wafers. Thus, overall cost can be reduced by using electroless deposition. However, electroless deposition requires the activation of a surface in order to electrolessly deposit the copper. (See for example, U.S. Pat. No. 4,574,095; "Electroless Copper Deposition on Metals and Silicides;" Cecilia Y. Mak; MRS Bulletin; August 1994; pp. 55-62; and "Development Of An Electroless Copper Deposition Bath For Via fill Applications On TiN Seed Layers;" Palmans et al.; Conference proceedings, ULSI-X, Materials research Society; 1995; pp. 87-94). Furthermore, since copper interconnects require isolation from adjacent material, the electroless deposition of copper must usually be performed on a barrier layer. Thus, where activation is required to electrolessly deposit copper, such activation will need to be performed on a barrier layer (such as TiN) or on a seed metal residing above such a barrier layer, in order to isolate the copper from the surrounding dissimilar material.
The present invention describes a technique of utilizing electroless metallization to form copper interconnect structures by employing copper as an activation agent on a barrier metal to initiate the autocatalytic process in fabricating multilevel semiconductor devices.